The present invention relates to a capacitive load element, and more particularly to a capacitive load element of an oscillator.
Phase locked loop (PLL) is an indispensable module of a transmission system, mainly for providing clock required for the operation of the system. Generally speaking, a PLL includes a frequency phase detector, a loop filter, an oscillator, and a frequency divider. According to different circuit implementations, a PLL can be classified into an analog PLL and a digital PLL.
In an analog PLL, a linear frequency phase detector compares frequency errors and phase errors between a reference clock and a loop-generated clock, and converts the errors into a voltage output. To stabilize the system and filter high-frequency environmental noises, a loop filter is employed to filter the voltage output. Afterwards, an oscillator adjusts the oscillation frequency according to the output voltage of the filter. When the analog PLL is applied to a system with a reference clock several or tens times larger, a frequency divider is added to divide the frequency of the clock output by the oscillator.
In a digital PLL, a non-linear frequency phase detector only detects the phase lead and phase lag and outputs a one-bit logic 1 or 0, instead of using different output voltages to represent various phase errors. A digital filter consisting of an adder, a multiplier, and a register is used as a loop filter. A digital control oscillation loop is adopted as an oscillator. And the operation and architecture of a frequency divider is identical to those of the analog PLL.
The filter of the analog PLL is formed by passive capacitors and resistors with fixed parameters, so the performance of the system is hard to regulate, and the lock time is long. Further, as a module circuit generally consists of a differential pair and current-source analog circuit, the size of the circuit must be repeatedly adjusted and verified, which increases the complexity in design. However, an analog oscillator has excellent clock precision and high oscillation frequency. The operation of the oscillator is approximately classified into a high-frequency single-phase mode and a low-frequency multi-phase mode. The former is provided by an LC tank oscillator, and the latter is provided by a ring oscillator formed by a delay buffer circuit.
Generally, the digital PLL achieves the purpose of fast-lock by means of binary search. Parameter flexibility of the architecture of the loop filter may be updated by updating the register, and meanwhile the circuit performance may be updated and improved by different types of standard cell libraries. Therefore, the digital architecture has high system integration and high update speed. However, the performance of digital PLL is limited by the digital control oscillator and cannot be applied to a relative high-speed transmission system. According to documents about the current digital control oscillator, the oscillation cycle has a propagation delay of tens logic gates, and the obtained minimum time resolution is a propagation delay of about 0.1 logic gate. Further, the current digital control oscillator cannot provide a multi-phase output. As for an element provided by a 0.18 μm process, the clock resolution is about several ps, and the generated clock jitter is about hundreds of ps, so the element can only be applied in a low-speed transmission system with a transmission speed of about several MHz to tens MHz.
Due to the improvement of the digital circuit process and in the trend of system on chip, a high-speed digital circuit is employed to replace a part of the analog circuit module, so as to enhance the system integration and reduce the circuit cost. Therefore, in order to make a clock supply system easier to update and regulate, the digital PLL is an optimal choice.